Resource Persons

Department of Electrical Engineering,
Indian Institute of Technology Bombay,
Powai, Mumbai 400076 India,
+91-22-2576-9432 (O)

Dr. Virendra is professor in Department of Electrical Engineering at Indian Institute of Technology, Bombay since 2011. He also served as a Faculty member at SERC, Indian Institute of Science (IISc), Bangalore from (May 2007 – Dec 2011), Banasthali University from (Jun 1996 – Mar 1997) and as a Scientist at Central Electronics Engg. Research Institute (CEERI), Pilani from (Mar 1997 – May 2007).
He received his doctorate in (Computer Science) from Nara Institute of Science and Technology (NAIST),Japan and Master’s from Malaviya National Institute of Technology (MNIT),Jaipur in Electronic and Telecommunication Engineering.
His area of Interest includes Computer Architecture, High performance processor design, verification and test, VLSI Testing, Fault tolerant computing, Dependable Architectures and Systems, Design for Reliability, Trusted Systems and Embedded Systems.

Abstract: Testing is an integral part of the VLSI design cycle. With the advancement in IC technology, designs are becoming more and more complex, making their testing challenging. Testing occupies 60-80% time of the design process. A well structured method for testing needs to be followed to ensure high yield and proper detection of faulty chips after manufacturing. Design for testability (DFT) is a matured domain now, and thus needs to be followed by all the VLSI designers.[1]
This talk will addresses important aspects most recent, yet fundamental, VLSI test principles and DFT architectures in an effort to help them design better quality products that can be reliably manufactured in large quantity.


Mr. Damodar Sambashiva,
Business Head,
Entuple Technologies, Bangalore.

Mr. Damodara is Business head at Entuple Technologies, Bangalore. He has over 19 years of industry experience with core expertise in Front end design and verification, Board System design with experience in telecom equipment, medical systems, aero-space automation & automotive hardware system design. His career spanned across organizations – Alcatel-Lucent (Bell Labs), Wipro, Altera. Also worked with Xilinx and Mentor Graphics customers (corporate and defense), supported Xilinx University Program and Mentor Higher Education Program.
He contributed in developing learning solutions in the space of RTL Design, Verification, Timing Analysis, System Design and more as a subject matter expert. Received appreciation award for his contribution in competency building initiatives for internal engineering resources at Wipro Technologies. Currently he is supporting IEEE in educational activities.
He is actively assisting Electronic Sector Skill Council of India (ESSCI) in developing National Skill Qualification Framework (NSQF) for engineering job profiles in VLSI domain. Mr. Damodara holds M.Tech in VLSI and Embedded Systems specialization from Visveswaraya Technological University, Karnataka and B.E (Bachelor of Engineering) in Electronics and Communication stream from Bangalore University.

Abstract: Digital IC development goes through multiple transformations from the original set of specifications to the final desired product. Each of these transformations corresponds, coarsely, to a different description of the system, which is incrementally more detailed and which has its own specific semantics and set of primitives.
This talk will cover a high level overview of this design flow of HDL Verification using Incisive as well as understanding role of Coverage Analysis in Verification.


Mr. Harish K ,
Field Engineer,
Entuple Technologies, Bangalore

Mr. Harish is consultant for customers across India from academic sector. Prior to joining Entuple technologies, he was with Sarvakarma solutions as Design Verification trainee engineer . He was actively involved in all activities supporting Verilog , System Verilog and UVM work groups. He also supported with different projects related to protocols. Harish Carries 8 months of training experience with core expertise in front end design and verification. His career spanned across organisations – Sarvakarma solution strained as Design Verification engineer by expertise engineers and at Entuple technologies as field application Engineer. He contributed in developing learning solutions in the space of RTL design, Verification and more as subject matter expert.
He holds Bachelor degree in Electronics and Communication stream from SSIT Tumkur, Karnataka.

Abstract: A hardware verification language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
Hardware Verification Languages (HVLs) specialized in giving verification engineers powerful constructs to describe stimulus and verify functionality in a much more concise manner.
This talk will focus on need for HVL based verification and advantages of HVL Methodology over Verilog HDL along with demonstration of the HVL based design flow on Incisive Software.


Mr. Sumit Patil,
Senior Application Engineer,
Entuple Technologies, Pune

Mr. Sumit is working as Sr. Application Engineer-Cadence at Entuple Technologies based out of PUNE, India. He is primarily responsible for application engineering and consultation for customers across India from Defense, aerospace and Corporate sector.

Prior to joining Entuple Technologies, was associated with many EDA companies like Trident,NI2 as technical expert. He carries over 10 years of industry experience with core expertise in Back end design and physical verification, physical design and Board System design and worked in major industry standard EDA tools in backend ASIC. He Was associated in projects in ASIC physical designing and physical verification based designs in major DRDO lab. He posseses expertise in HDL coding ,physical design, analog layout, verification and backend design, EMI, EMC, RF, Antenna. Cadence and Mentor Graphics Toolsets.
He holds B.Tech degre in VLSI from VIT Electronics stream from Pune University.

Abstract: Simulation might be caricatured as the process of poking test vectors into a model of the design-under-test and observing how that model behaves. A traditional Verilog or VHDL test bench might contains processes to read raw vectors or commands from a file, use those to change the values of the wires connected to the DUT over time, and perhaps collect output from the DUT and dump it to another file. This is fine as far as it goes, but this process does not scale up well to support the reliable verification of very complex systems.
Functional checking must be automated if the process is to scale well, as must the collection of verification metrics such as the coverage of features in the verification plan and the number of bugs found by each test. Along with the verification plan, automated checking and functional coverage collection and analysis are cornerstones of any good verification methodology, and are explicitly addressed by SystemVerilog and UVM.
This talk will address some core aspects of evolvement of the UVM, Design flow and Demonstration of the UVM Constructs.


Mr. Pawankumar Fakatkar,
Education Technical Evangelist,
MathWorks, Pune

Mr. PawanKumar is working as Education Technical Evangelist at Mathworks, Pune. At Mathworks, he work on development of the Application involving hardware interfacing with Matlab(Hardware in Loop), Deep learning algorithm, Neural Networks, Face detection, Autonomous vehicle navigation etc. Before joining Mathwork, he worked as an Assistant Professor at Sardar Patel Institute of Technology.
He completed his Master’s from Sardar Patel Institute of Technologyin Electronic and Telecommunication Engineering and Electronics Engineering from Terna College of Engineering, Mumbai.

Abstract: Thorough and reliable tests are necessary to verify and validate design. But, as modern systems grow in complexity, particularly in software, this critical step is more easily said than done.
Consider testing the electronic components of a new car. To remain relevant in today’s market, modern vehicles need to include advanced driver-assistance systems (ADAS), cameras, radar, and more. Testing these subsystems on the assembled product in desired use cases ensures that testing is performed in the ideal context, but it also incurs significant test overhead and the challenge of testing every scenario. Additionally, delaying tests until final assembly carries significant risk, and test-driven changes can lead to catastrophic schedule impacts. Unthinkable test cost and an unpredictable time to market are sure to follow. These factors sound like the makings of an impossible problem calling into question the plausibility of thorough testing that is both cost and time effective.
The solution must provide comprehensive testing without the burden of using an assembled final product in the field. By allowing ECUs under test to interact with a simulated use case, you are free to test early and often to uncover as many software defects as possible. This is the basis of a hardware-in-the-loop (HIL) test.


Prof. Mrugendra Vasmatkar,
Assistant Professor,
Vivekanand Education Society’s Institute of Technology,

Prof. Mrugendra has over 3.3 years of experience in EDA/VLSI technology. He worked as Team Lead Verification and Testing at Powailabs Technology Pvt. Ltd, where he developed an IMAGE (Emulator) capable of taking a specified design description and map it to the hardware consisting of multiple FPGAs and memory. He possesses expertise and several years of experience in Hardware Description Languages and MATLAB.
He completed his Master’s from Shri Guru Gobind Singhji Institute of Engineering and Technology, Nanded Engineering and Bachelor degree from the Shyamlal College of Engineering, Latur in Electronics Engg. He is currently working as Assistant Professor in Electronics and Telecommunication Engineering Department of Vivekanand Education Society’s Institute of Technology.

Abstract: The Xilinx® MicroBlaze™ IP core is a highly configurable 32-bit microprocessor optimized for the programmable logic in Xilinx FPGAs and SoCs. Seamlessly integrated into the Xilinx Vivado® design environment, power users can leverage the MicroBlaze processor to create a customized, high-performance, SoC-based system. Alternatively, Xilinx provides a preconfigured MicroBlaze core with the most-used microcontroller, real-time, and application software presets, enabling the designer to get started with software development right away using freely available evaluation PC boards.
This talk will address design flow for Microblaze based FPGA System design along with the Demonstration and implementation of the Microblaze based design on Block design editor of the Vivado Design suite utilizing Digilent Zybo FPGA Development Board.


Dr. S. S. Rathod,
Dean Academics, Professor & Head,
Sardar Patel Institute of Technology,
Phone: +91-22-26287250 Ext: 350

Dr. S. S. Rathod received his doctorate degree in VLSI Design from IIT Roorkee. He has over 20 years of teaching experience. His special fields of interest include VLSI system Design and Verification, Device modeling and Circuit simulation. He has published more than 50 papers in various national and international conferences and published 23 papers in international journals like Journal of applied physics, IEEE transactions on electron devices, Elsevier microelectronics reliability, IET circuit’s devices and systems, ASP journal of low power electronics etc. He is reviewer of IEEE transactions on Electron Devices, Elsevier Microelectronics Journal, Microelectronics Reliability, Academic Journal of Electrical and Electronics Engineering Research, Emrald International Journal of Electronics, Journal of scientific research and review, and several national and international conferences.
Abstract: SystemVerilog is perhaps most widely used in the context of hardware verification, it also contains many features directly relevant to the hardware designer.
SystemVerilog provides a complete verification environment, employing Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve dramatically the verification process. SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.
The talks addresses the fundamental principles of RTL coding style in SystemVerilog, OOP Approach, Interprocess communication, Randomization and Code Coverage.


Mr. Kumar Khandagle
Assistant Professor,
Sardar Patel Institute of Technology,
Phone: +91-9112434909

Mr. Kumar Khandagle is working as Assistant Professor in Electronics Department of the Sardar Patel Institute of Technology since last 2 Years. He worked as a Research Scientist at SAMEER(Society for Applied Microwave Electronics Engineering & Research), Mumbai on Design of Digital Gradient Controller for Indigenous Magnetic Resonance Imaging System.
Mr. Kumar is currently pursuing his Doctorate in Electronics Engineering. He hold his Master’s in Electronics Engineering from VJTI. Mumbai and Bachelor degree in Electronic and Telecommunication Engineering from RCPIT, Shirpur.

Abstract: Field-programmable gate arrays (FPGAs) are reprogrammable integrated circuits that contain an array of programmable logic blocks. FPGA chip adoption is driven by their flexibility, hardware-timed speed and reliability, and parallelism. Unlike processors, FPGAs are truly parallel in nature, so different processing operations do not have to compete for the same resources. Each independent processing task is assigned to a dedicated section of the chip and can function autonomously without any influence from other logic blocks. As a result, the performance of one part of the application is not affected when you add more processing.
This talk will focus on the Understanding of Hardware Description language used to build system on FPGA’s with majority of focus on understanding Modeling, Synthesis, Functional Verification, Implementation and floor planning on Xilinx Vivado and ISE Design Suite.