About

About the STTP

The Front end VLSI design has achieved tremendous growth in worldwide markets since last few decades. There is a significant gap between the actual requirements of industry and the knowledge imparted in academics about the Physical System Implementation on FPGA and their verification strategies. It is very important and necessary to share the experiences of FPGA Design flow and Verification from the experts. There is a need for upgradation of the curriculum to enhance skills in Physical Design Implementation and Verification.
Through this Short term training program we aim to bring the industry expertise to the doors of academia to develop Physical Design, Implementation and Hardware Verification skills necessary to effectively accomplish design of VLSI Systems. Candidates will gain hands-on experience on Xilinx family FPGA’s and also on Cadence Tool-sets.

Objectives of the STTP

  1. Identification of challenges in VLSI System design, Functional testing and Hardware verification.
  2. Development of trained resources in VLSI System design and verification.
  3. To acquire insights about technological details of VLSI system Design flow from industry experts
  4. To motivate teachers to develop curriculum and pedagogy for VLSI System Design and Verification.
  5. To discuss the methodologies of selection of particular families of FPGA for specific application to reduce design complexity.

 

Benefits to Faculty
Through this Short term training program we aim to bring the industry expertise to the doors of academia to develop Physical Design, Implementation and Hardware Verification skills necessary to effectively accomplish design of VLSI Systems. Candidates will gain hands-on experience on Xilinx family FPGA’s and Cadence tool-set. Also the fundamental knowledge of SystemVerilog will be imparted during the course.

Expected Outcome

  1. Manpower development in the area of design of Front End VLSI Design and Verification. Interaction among peers in the field of Physical Design and Verification.
  2. Course material on VLSI System Design Flow.
  3. Development of learning material for Design flow in Front End VLSI.
  4. Sharing of knowledge among participants about innovative VLSI Technologies.
  5. Hands-on training with Xilinx 7-series FPGA.

Course Contents/Highlights
Broadly one week STTP will cover following contents:

  • Verilog Hardware Description language
  • Synthesis and Physical Implementation
  • Implementation on Zybo and Nexys-4 DDR
  • Using Microblaze Soft Core
  • Fundamentals of Verification
  • SystemVerilog Fundamentals
  • Object Oriented Programming in Verification
  • Advanced verification concepts like Randomization, Inter Process Communication, Code Coverage and Assertion
  • Testbench writing using SystemVerilog
  • Various Toolsets for Verification

Teachers from AICTE recognized engineering colleges and polytechnics can attend this seminar.

Resource Persons

Distinguished faculty members from the renowned institutes like IIT, industries and other institutes will be the resource persons for the Seminar.