STTP1: Digital VLSI Design and Verification
STTP2: Analog CMOS VLSI Design
STTP3: Mixed Signal VLSI Design
About the STTPs
VLSI design has achieved tremendous growth in worldwide markets since last few decades. There is a significant gap between the actual requirements of industry and the knowledge imparted in academics on the industry grade toolsets. The main objective of this training is to provide information through demonstrations of digital and analog blocks. Theoretical background will be supported by demonstrations on various simulation tools including Cadence toolsets. The aspects of Digital VLSI Design, Analog VLSI Design, Mixed Signal Design, various analysis, layout, DRC, Layout versus Schematic, parasitic extraction, post layout simulation to be demonstrated in the course. Through this STTP we aim to give information which is necessary to effectively accomplish design of VLSI Systems. This STTP also aims to share the experiences of professionals working in the domain of VLSI Design.
Objectives of the STTP
- Identification of challenges in VLSI design and simulation of digital and analog circuits.
- Development of trained resources in VLSI design.
- To acquire insights about technological details of VLSI system Design flow from industry experts
- To motivate teachers to develop and curriculum and pedagogy for VLSI Design.
- To provide information about tools used in VLSI Industry
- Manpower development in the area of design of Front End and back end VLSI Design
- Interaction among peers in the field of Physical Design and Verification.
- Course material related to VLSI Design on concepts taught during course
- Development of laboratory exercises related to digital, analog & mixed signal CMOS VLSI design
- Sharing of knowledge among participants about advanced VLSI design concepts
- Exposure to industry standard toolsets for digital, analog and mixed Signal design
Broadly one week STTP will cover following contents:
- Introduction to VLSI and Industry Overview
- VLSI Design Flow
- Invited talks delivered by experts from industry and academic organizations
- Demonstrations through simulations.
- STTP1: Digital VLSI Design and Verification
- ASIC design flow, Modeling using Verilog, Function simulation to Synthesis. Simulation and analysis using Cadence incisive simulator. Circuit simulation, layout capture and LVS verification, Physical Design and Verification Overview. Basics of CMOS digital design, Case studies and research challenges.
- STTP2: Analog CMOS VLSI Design
- Characterization of Analog Model Parameters, Single Stage Amplifier Circuit Topologies, Diff-Amp and Op-Amp Design, Exposure to Cadence Virtuoso Analog Design Environment
- STTP3: Mixed Signal VLSI Design
- Fundamentals of Mixed Signal Design with Examples, Case studies, Exposure to simulation toolset for mixed signal design
Teachers from AICTE recognized engineering colleges and polytechnics can attend this STTP.
Distinguished faculty members from the renowned institutes like IIT, other institutes and industry will be the resource persons for the STTP.
Cadence Tool Access
Optional access to Cadence tools for hands-on session may be provided by Entuple to interested participants on payment basis. For this please contact Entuple Representatives.